This invention relates to semiconductor memories, and more particularly to a method of manufacturing and a structure of a split-gate non-volatile memory cell which provides a simple and highly accurate means of controlling the cell channel length which is a critical parameter for proper cell operation.
A conventional method of defining a select gate transistor in a non-volatile memory cell (e.g., in a split-gate cell) is to use a second layer polysilicon masking step along with a second layer polysilicon etching step. The masking and etching steps define a predetermined second layer polysilicon length and a corresponding portion of the cell channel length. The channel length of a split-gate cell is typically made-up of a portion under the floating gate plus another portion under the second polysilicon spacer side-wall.
As the channel length of split-gate cells continue to shrink in submicron technologies, it becomes increasingly difficult to accurately define the channel length because the polysilicon spacer side-wall starts to define a larger portion of the total channel length. For example, a deposited second layer polysilicon film with a thickness of 2,500 xc3x85 creates a spacer width of about 0.25 xcexcm. If the total channel length target is 0.35 xcexcm and the floating gate portion of the channel is 0.25 xcexcm, it leaves the second layer polysilicon lithography step a misalignment tolerance relative to floating gate edges of a mere 0.05 xcexcm.
In another case where the second polysilicon spacer width is 0.25 xcexcm, if the target length for the portion of the channel length defined by the second polysilicon spacer is 0.2 xcexcm, a very long over-etch is required to remove the twice-greater thickness of the second polysilicon film along the spacer region (the twice-greater thickness is caused by the step in second polysilicon due to the presence of the floating gate). This over-etch step, which is also carried out in the periphery CMOS region of the memory device wherein the twice-greater thickness of second polysilicon is not present, can severely pit the silicon in the source and drain junction regions of the periphery transistors. The silicon pitting causes an undesirable leakage current from the source and drain regions to the substrate. Further, such over-etch of the second layer polysilicon in the periphery CMOS regions makes the control of critical dimension (CD) in the periphery region more difficult. A solution to the CD control problem and the silicon pitting is to use a separate mask for etching of the second layer polysilicon in the periphery than that used in the array. But, the additional mask results in a more costly process.
Thus, a method of manufacturing and a structure of a non-volatile semiconductor memory cell which provides a simple and highly accurate means of controlling a sub-micron channel length, without requiring additional masking steps or over-etching of the second layer polysilicon film, is needed.
In accordance with an embodiment of the present invention, a method of forming a memory cell includes: forming a floating gate over a first portion of a silicon body region, the floating gate being insulated from the underlying first portion of the body region; forming a second layer polysilicon over the floating gate and a second portion of the body region, the second layer polysilicon being insulated from the underlying floating gate and the second portion of the body region; and forming a masking layer over the second layer polysilicon, the masking layer having a width along a first dimension parallel to the surface of the body region such that the masking layer extends over an entire width of the floating gate along the first dimension but does not extend beyond edges of steps of the second layer polysilicon formed due to the presence of the floating gate.
In one embodiment, the method further includes performing an etch cycle so that the portions of the second layer polysilicon not covered by the masking layer are etched back by an amount substantially equal to a predefined thickness of the second layer polysilicon.
In another embodiment, in a memory device having an array region and a periphery region, the second layer polysilicon in the array region also forms polysilicon gates of transistors in the periphery region, the etch cycle being designed to achieve a target critical dimension (CD) for a polysilicon gate length of the periphery transistors.
In another embodiment, the method further includes forming a source region and a drain region in the body region so that an inner edge of each of the source and drain regions is self-aligned to a corresponding outer edge of two second layer polysilicon spacers formed adjacent floating gate side-walls as a result of the etch cycle.
In another embodiment, a portion of the body region bounded by the source and drain regions forms a channel region having a channel length, a width of each of the second layer polysilicon spacers along the first dimension defining a corresponding portion of the channel length.
In another embodiment, the portions of the channel length corresponding to the spacers are symmetrical about the floating gate.
The following detailed description and the accompanying drawings provide a better understanding of the nature and advantages of the present invention.